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Some Search Engines are not showing the Source Code of the Page.This invention relates to a method and apparatus for preventing errors in the execution of arithmetic and logical operations in a microprogrammed central processing unit (CPU) or a microprocessor, and in particular, to a microprogrammed method and apparatus for reducing the number of traps generated in the microcode (fetch and execute) and for reducing the number of execution stalls.
FIG. 1 illustrates the structure of a typical prior art (fetch and execute) microprogrammed CPU.
As shown in FIG. 1, the CPU includes a control section 111, an instruction memory 110 for storing instruction data, a register file 120 for storing operand data (a) to (n), a decode section (decoder) 112 for decoding the instruction data in the instruction memory 110, a data memory for storing the operand data which have been decoded by the decode section 112, an arithmetic and logical operation section (ALU) 113 for performing an arithmetic and logical operation, a writeback section 114 for writing a result of the operation into the register file 120, a write data memory 115 for writing the result of the operation into the register file 120, a shift section 116 for shifting the data memory and the register file and a buffer 117 for buffering the instruction data which are inputted from the control section 111.
The data memory is located outside the CPU and stored the operand data which are needed to execute the instruction. For example, a data memory provided in the instruction memory 10 stores the operand data which are needed to execute the instruction. The instruction data are the data which are written in the instruction memory 110 and are decoded by the decode section 112. The instruction data are fetched from the memory and supplied to the arithmetic and logical operation section 113 and are executed by the ALU 113.
Further, the register file 120 stores the operand data for the arithmetic and logical operation which are provided from the arithmetic
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